www.lansdale.com page 1 of 8 issue a ML145407 5 volt only driver/receiver rs232 eia?32? and ccitt v.28 legacy device: motorola mc145407 the ML145407 is a silicon?ate cmos ic that combines three drivers and three receivers to fulfill the electrical specifications of rs232 eia?32? and ccitt v.28 while operating from a single + 5 v power supply. a voltage doubler and inverter convert the + 5v to 10 v. this is accomplished through an on?oard 20 khz oscillator and four inexpensive external electrolytic capacitors. the three drivers and three receivers of the ML145407 are virtually identical to those of the ml145406. therefore, for applications requiring more than three drivers and/or three receivers, an ml145406 can be powered from an ML145407, since the ML145407 charge pumps have been designed to guarantee 5 v at the output of up to six drivers. thus, the ML145407 provides a high?erformance, low?ower, stand?lone solution or, with the ml145406, a + 5 v only, high?erformance two?hip solution. this device offers the following performance features: ? operating temperature range = t a ?0 to +85? drivers ? 7.5 v output swing ? 300 power?ff impedance ? output current limiting ? ttl and cmos compatible inputs ? slew rate range limited from 4 v/? to 30 v/? receivers ? + 25 v input range ? 3 to 7 k input impedance ? 0.8 v hysteresis for enhanced noise immunity charge pumps ? + 5 v to 10 v dual charge pump architecture ? supply outputs capable of driving three on?hip drivers and three drivers on the ml145406 simultaneously ? requires four inexpensive electrolytic capacitors ? on?hip 20 khz oscillator p dip 20 = rp plastic dip case 738 sog 20 = -6p sog package case 751d 20 1 20 1 cross reference/ordering information motorola p dip 20 mc145407p ML145407rp sog 20 mc145407dw ML145407-6p lansdale package note : lansdale lead free ( p b ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . r r d r d d c2+ gnd c2 v ss rx1 tx1 rx2 tx2 rx3 tx3 c1+ v cc c1 v dd do1 di1 do2 di2 do3 di3 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 pin assignment d = driver r = receiver
www.lansdale.com issue a lansdale semiconductor, inc. ML145407 page 2 of 8 tx function diagram v dd v cc di 1.4 v v ss 300 level shift driver * v cc osc voltage doubler voltage inverter c3 v dd c1 c1 c1 + c2 c2 + c2 v ss gnd c4 + + + + v cc do 1.0 v 1.8 v v ss rx v dd 5.4 k 15 k v dd * proctection circuit receiver charge pumps + +
www.lansdale.com page 3 of 8 issue a lansdale semiconductor, inc. ML145407 maximum ratings (voltage polarities referenced to gnd) rating symbol value unit dc supply voltages v cc ?0.5 to + 6.0 v input voltage range rx1 ?rx3 inputs di1 ?di3 inputs v ir v ss ?15 to v dd + 15 ?0.5 to (v cc + 0.5) v dc current per pin i 100 ma power dissipation p d 1 w operating temperature range t a ?40 to + 85 c storage temperature range t stg ?85 to + 150 c dc electrical characteristics (all polarities referenced to gnd = 0 v; c1, c2, c3, c4 = 10 f; t a = ?40 to + 85 c) parameter symbol min typ max unit dc supply voltage v cc 4.5 5 5.5 v quiescent supply current (outputs unloaded, inputs low) i cc 1.2 3.0 ma output voltage i load = 0 ma i load = 5 ma i load = 10 ma v dd 8.5 7.5 6 10 9.5 9 11 v i load = 0 ma i load = 5 ma i load = 10 ma v ss ?8.5 ?7.5 ?6 ?10 ?9.2 ?8.6 ?1 receiver electrical specifications (voltage polarities referenced to gnd = 0 v; v cc = + 5 v 10%; c1, c2, c3, c4 = 10 f; t a = ?40 to + 85 c) characteristic symbol min typ max unit input turn?n threshold rx1 ?rx3 v do1 do3 = v ol v on 1.35 1.8 2.35 v input turn?ff threshold rx1 ?rx3 v do1 do3 = v oh v off 0.75 1.0 1.25 v input threshold hysteresis (v on ?v off ) rx1 ?rx3 v hys 0.6 0.8 v input resistance rx1 ?rx3 r in 3.0 5.4 7.0 k high?evel output voltage do1 ?do3 v rx1 rx3 = ?3 v to ?25 v i oh = ?20 a i oh = ?1 ma v oh v cc ?0.1 v cc ?0.7 4.3 v low?evel output voltage do1 ?do3 v rx1 rx3 = + 3 v to + 25 v i ol = + 20 a i ol = + 1.6 ma v ol 0.01 0.5 0.1 0.7 v this device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high imped- ance circuit. for proper operation, it is recom- mended that the voltages at the di and do pins be constrained to the range gnd v di v cc and gnd v do v cc . also, the voltage at the rx pin should be constrained to (v ss ?15 v) v rx1 rx3 (v dd + 15 v), and tx should be constrained to v ss v tx1 tx3 v dd . unused inputs must always be tied to appropriate logic voltage level (e.g., gnd or v cc for di, and gnd for rx).
www.lansdale.com page 4 of 8 issue a lansdale semiconductor, inc. ML145407 driver electrical specifications (voltage polarities referenced to gnd = 0 v: v cc = +5 v 10%; c1, c2, c3, c4 = 10 f; t a = 40 to +85 c) characteristic symbol min typ max unit digital input voltage di1 ?di3 logic 0 logic 1 v il v ih 2.0 0.8 v input current di1 ?di3 gnd v di1 di3 v cc i in 1.0 a output high voltage tx1 ?tx3 v di1 di3 = logic 0, r l = 3.0 k tx1 ?tx6* v oh 6 5 7.5 6.5 v output low voltage tx1 ?tx3 v di1 di3 = logic 1, r l = 3.0 k tx1 ?tx6* v ol ?6 ?5 ?7.5 ?6.5 v off source impedance (figure 1) tx1 ?tx3 z off 300 output short?ircuit current tx1 ?tx3 v cc = + 5.5 v tx1 ?tx3 shorted to gnd** tx1 ?tx3 shorted to 15 v*** i sc 60 100 ma * specifications for an ML145407 powering an ml145406 with three additional drivers/receivers. ** specification is for one tx output pin to be shorted at a time. should all three driver outputs be shorted simultaneously, de vice power dissipation limits could be exceeded. *** this condition could exceed package limitations. switching characteristics (v cc = + 5 v 10%; c1, c2, c3, c4 = 10 f; t a = ?40 to + 85 c; see figures 2 and 3) characteristic symbol min typ max unit drivers propagation delay time tx1 ?tx3 low?o?igh r l = 3 k , c l = 50 pf or 2500 pf t plh 0.5 1 s high?o?ow r l = 3 k , c l = 50 pf or 2500 pf t phl 0.5 1 output slew rate tx1 ?tx3 minimum load: r l = 7 k , c l = 0 pf sr 9.0 30 v/ s maximum load: r l = 3 k , c l = 2500 pf 4.0 receivers (c l = 50 pf) propagation delay time do1 ?do3 low?o?igh t plh 1 s high?o?ow t phl 1 output rise time do1 ?do3 t r 250 400 ns output fall time do1 ?do3 t f 40 100 ns
www.lansdale.com page 5 of 8 issue a lansdale semiconductor, inc. ML145407 pin d e scriptions v cc digital power supply (pin 19) the digital supply pin, which is connected to the logic pow- er supply. this pin should have a 0.33 ? capacitor to ground. gnd ground (pin 2) ground return pin is typically connected to the signal ground pin of the eia?32? connector (pin 7) as well as to the logic power supply ground. v dd positive power supply (pin 17) this is the positive output of the on chip voltage doubler and the positive power supply input of the driver/receiver sections of the device. this pin requires an external storage capacitor to fil- ter the 50% duty cycle voltage generated by the charge pump. v ss negative power supply (pin 4) this is the negative output of the on?hip voltage doubler/inverter and the negative power supply input of the driver/receiver sections of the device. this pin requires an external storage capacitor to filter the 50% duty cycle voltage generated by the charge pump. c2+, c2? c1? c1+ voltage doubler and inverter (pins 1, 3, 18, 20) these are the connections to the internal voltage doubler and inverter, which generate the vdd and vss voltages. rx1, rx2, rx3 receive data input (pins 5, 7, 9) these are the eia?32? receive signal inputs. a voltage between + 3 and + 25 v is decoded as a space and causes the corresponding do pin to swing to ground (0 v). a voltage between ?3 and ?25 v is decoded as a mark, and causes the do pin to swing up to vcc. do1, do2, do3 data output (pins 16, 14, 12) these are the receiver digital output pins, which swing from v cc to gnd. each output pin is capable of driving one lsttl input load. di1, di2, di3 data input (pins 15, 13, 11) these are the high impedance digital input pins to the driv- ers. input voltage levels on these pins must be between v cc and gnd. tx1, tx2, tx3 transmit data output (pins 6, 8, 10) these are the eia?32? transmit signal output pins,which swing toward v dd and v ss . a logic 1 at a di input causes the corresponding tx output to swing toward v ss . a logic 0 caus- es the output to swing toward v dd . the actual levels and slew rate achieved will depend on the output loading (rl\\cl). v in = 2v 6 8 10 15 13 11 42 17 19 v dd v cc di1 di2 di3 v ss gnd tx3 tx2 tx1 r out = v in i figure 1. power?ff source resistance figure 2. switching characteristics figure 3. slew rate characterization drivers di1 ?di3 3 v 0 v v oh v ol tx1 ?tx3 t plh t phl 50% t f t r 10% 90% receivers rx1 ?rx3 do1 ?do3 + 3 v 0 v v oh v ol t plh t phl t f t r 50% drivers tx1 ?tx3 90% 50% 3 v ?3 v 3 v ?3 v t shl t slh slew rate (sr) = 3 v ?(3 v) or 3 v ?( 3 v) t slh t shl 10%
www.lansdale.com page 6 of 8 issue a lansdale semiconductor, inc. ML145407 e sd consid e rations esd protection on ic devices that have their pins accessible to the outside world is essential. high static voltages applied to the pins when someone touches them either directly or indi- rectly can cause damage to gate oxides and transistor junctions by coupling a portion of the energy from the i/o pin to the power supply busses of the ic. this coupling will usually occur through the internal esd protection diodes. the key to protecting the ic is to shunt as much of the energy to ground as possible before it enters the ic. figure 7 shows a technique which will clamp the esd voltage at approximately + 15 v using the mmbz15vdlt1. any residual voltage which appears on the supply pins is shunted to ground through the 0.1 ? capacitors. op e ration with small e r valu e charg e pump caps the ML145407 is characterized in the electrical tables using 10 ? charge pump caps to illustrate its capability in driving a companion ml145406 or ml145403. if there is no require- ment to support a second interface device and/or the charge pump is not being used to power any other components, the ML145407 is capable of complying with eia?32? and v.28 with smaller value charge pump caps.table 1 summarizes driv- er performance with both 2.2 ? and1.0? charge pump caps. 14 600 16 tip 13 bypass dtmf input r dsi 20 k c dsi rtla + 5 v 20 6 9 8 3 11 5 tla dsi txa rxa2 1 17 15 v dd x in x out cd txd rxd sqt lb mode cda v ss cdt v ag fb exi rxa1 r tx 18 10 19 4 600:600 c fb + 10 k ring v dd v dd bypass v ss c cdt 12 7 2 10 k 10 k 10 k 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 1.0 f 3.579 mhz c cda 3 1 15 16 13 17 19 6 5 8 7 9 8 2 3 7 2 4 v ss gnd di3 di2 do1 di1 c2 + c2 v dd v cc c1 c1 + tx1 rx1 tx2 rx2 rx3 * line protection circuit ml145442 or ml145443 ML145407 1.0 f 1.0 f 1.0 f + eia?32? db?5 connector 0.1 f 0.1 f 0.1 f * figure 4. 5 v, 300 baud modem with eia?32? interface table 1. typical performance parameter 2.2 f 1.0 f tx v oh @ 25 c 7.3 7.2 tx v oh @ 85 c 7.2 7.1 tx v ol @ 25 c 6.5 6.4 tx v ol @ 85 c 6.1 6.0 tx slew rate @ 25 c 8.0 v/ s 8.0 v/ s tx slew rate @ 85 c 7.0 v/ s 7.0 v/ s
www.lansdale.com page 7 of 8 issue a lansdale semiconductor, inc. ML145407 1 v dd v cc c1+ 20 c2+ 1 10 f ML145407 ml145406 2 3 4 5 6 7 89 10 11 12 13 14 15 16 2 3 4 5 6 7 8 11 12 13 14 15 16 9 10 17 18 19 rx1 tx1 rx2 tx2 rx3 tx3 v ss do1 di1 do2 di2 do3 di3 gnd gnd c2 v ss rx1 tx1 rx2 tx2 rx3 tx3 di3 do3 di2 do2 di1 do1 v dd c1 v cc + 5 v 10 f 10 f 10 f figure 5. ml145406/ML145407 5 v only solution for up to six eia?32? drivers and receivers c1+ c1 v cc 0.1 f 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 c4 c2 c2+ gnd c2 v ss v dd 0.1 f + 10 v + 5 v figure 6. two supply configuration (ML145407 generates v ss only) c1+ c1 do1 di1 do2 di2 do3 di3 v cc 0.1 f 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 to connector mmbz15vdlt 6 9 12 10 11 c4 c2 c2+ gnd c2 rx1 tx1 rx2 tx2 rx3 tx3 v ss v dd 0.1 f c3 c1 + 5 v figure 7. esd protection scheme
www.lansdale.com page 8 of 8 issue a lansdale semiconductor, inc. ML145407 outline dimensions p dip 20 = rp plastic dip (ML145407rp) case 738?3 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e gf d 20 pl j 20 pl l m -t- seating plane 1 10 20 11 0.25 (0.010) t a m m 0.25 (0.010) t b m m b sog 20 = -6p sog package (ML145407-6p) case 751d?4 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ? seating plane m r x 45 dim min max min max a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil- ity, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical?parameters whi ch may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by the cus- tomer s technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc.
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